1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a memory array such as a dynamic random access memory (DRAM) and a peripheral circuit such as a logic circuit and to a method of making the same.
2. Description of the Related Art
In order to process and display video signals at a high speed for a personal computer or a game machine, there is a demand for a one-chip semiconductor device having a high speed logic integrated circuit and a high capacity DRAM. This is to avoid a reduction of the processing speed. A two-chip type device composed of a DRAM chip and a logic IC chip has the disadvantage of not being able to send a large amount of data simultaneously between the DRAM and logic IC due to the limits imposed by its bus width.
On another matter, in the future, it will be necessary to lower the resistance of the diffusion regions using the self-aligned silicide technique to improve the performance of the logic integrated circuit.
However, in the silicidation of the metal oxide semiconductor (MOS) switching transistor of a DRAM, there is the problem that the heat treatment for forming the bit lines after forming the self-aligned silicide and the heat treatment at the time of making the capacitors cause an increase of the resistance of the silicidated diffusion regions and greater junction leakage.
It is the object of the invention to provide a semiconductor device having a memory array such as a DRAM and a peripheral circuit such as a logic circuit which can improve the processing speed of the peripheral circuit without decreasing the data retention of the memory array.
According to one aspect of the invention, there is provided a semiconductor memory device comprising a memory array including memory cells; a peripheral circuit; and a covering conductive layer formed on the diffusion regions of the peripheral circuit but not formed on the diffusion regions of the memory array.
Also, according to another aspect of the invention, there is provided a process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on a single substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circuit; forming the memory cells; exposing the surfaces of the diffusion regions in the peripheral circuit after forming the memory cells; and forming a covering conductive layer on the exposed regions of the diffusion regions.
More specifically, the semiconductor device of the present invention has field effect transistors in the memory array and field effect transistors in the peripheral circuit, formed on the same substrate, has a covering conductive layer consisting for example of a metal or a metal alloy formed on the surface of the diffusion regions of the field effect transistors in the peripheral circuit, and does not have such a covering conductive layer on the surface of the diffusion regions of the field effect transistors forming the memory cells.
Therefore, since the memory cells are connected to diffusion regions not having a conductive layer such as a silicide, the semiconductor device of the present invention does not have the disadvantage of an increase of the junction leakage in the memory cells. Since the covering conductive layer is only formed on the diffusion regions of the transistors not comprising memory cells, the diffusion regions of the semiconductor device of the invention have a low resistance, so enable a high processing speed of the logic circuit and enable a high performance DRAM and a logic circuit having a high processing speed to be provided in a single chip device without any decrease of either performance.
According to the process for producing a semiconductor device of the invention, the peripheral circuit is covered by the interlayer insulating layer, the memory cells are formed, then the surface of the diffusion regions in the peripheral circuit is exposed, and a covering conductive layer is formed on the exposed diffusion regions in the peripheral circuit.
Therefore, since the memory cells are formed in diffusion regions with no covering conductive layer such as a silicide, the semiconductor device according to the process of the present invention does not have the disadvantage of an increase of the junction leakage in the memory cells. Since the covering conductive layer is formed on the diffusion regions of the peripheral circuit after forming the memory cells, there is no disadvantage of an increase of the resistance of the covering conductive layer, for example a silicide, due to the heat treatment at the time of forming the capacitors of the memory cells. Thus the semiconductor device of the process of the present invention exhibits a good data retention of the memory cells and a high processing speed in the peripheral circuit.